1. Field of the Invention
The present invention relates to a semiconductor chip mounting substrate, and more particularly, to the semiconductor chip mounting substrate in which a semiconductor bare chip is connected to a substrate by wire bonding.
2. Description of the Related Art
Recent years have seen a remarkable progress in the development of a display device using a flat display panel, and especially, a three-electrode surface-discharge AC flat display panel (PDP) is being put into practical use for and applied to a large-sized television set and so on since its screen can easily be made large and colorized.
FIG. 8 is a block diagram schematically showing a three-electrode surface-discharge plasma display panel of an AC drive type, and FIG. 9 is a cross sectional view explaining the electrode structure of the plasma display panel shown in FIG. 8. In FIG. 8 and FIG. 9, the reference numeral 207 denotes discharge cells (display cells), 210 a rear glass substrate, 211 and 221 dielectric layers, 212 phosphors, 213 barrier ribs, 214 address electrodes (A1 to Ad), 220 a front glass substrate, and 222 X electrodes (X1 to XL) or Y electrodes (Y1 to YL), respectively. Note that the reference symbol Ca shows capacity between adjacent electrodes in the address electrodes 214, and Cg shows capacity between opposing electrodes (the X electrode and the Y electrode) 222 in the address electrodes 214.
A plasma display panel 201 is composed of two glass substrates, the rear glass substrate 210 and the front glass substrate 220. In the front glass substrate 220, the X electrodes (X1, X2, to XL) and the Y electrodes (scan electrodes: Y1, Y2, to YL) constituted as sustain electrodes (including BUS electrodes and transparent electrodes) are disposed.
In the rear glass substrate 210, the address electrodes (A1, A2, to Ad) 214 are disposed to perpendicularly cross the sustain electrodes (the X electrodes and the Y electrodes) 222. Each of the display cells 207 generating discharge light-emission by these electrodes is formed in a region which is sandwiched by the X electrode and the Y electrode, namely the sustain electrodes, assigned the same number (Y1-X1, Y2-X2, . . . ) and which intersects the address electrode.
FIG. 10 is a block diagram showing the overall structure of a plasma display device using the plasma display panel shown in FIG. 8. It shows an essential part of a drive circuit for the plasma display panel.
As shown in FIG. 10, the three-electrode surface-discharge plasma display device of an AC drive type is composed of the display panel 201 and a control circuit 205 which generates control signals for controlling the drive circuit for the plasma display panel by an interface signal which is inputted from the outside. The three-electrode surface-discharge plasma display device of an AC drive type is also composed of an X common driver (an X electrode drive circuit) 206, a scan electrode drive circuit (a scan driver) 203, a Y common driver 204, and an address electrode drive circuit (an address driver) 202, which are to drive panel electrodes by the control signals from the control circuit 205.
The X common driver 206 generates a sustain voltage pulse. The Y common driver 204 also generates a sustain voltage pulse. The scan driver 203 independently drives and scans each of the scan electrodes (Y1 to YL). The address driver 202 applies an address voltage pulse corresponding to display data to each of the address electrodes (A1 to Ad).
The control circuit 205 includes a display data control part 251 which receives a clock CLK and display data DATA and supplies an address control signal to the address driver 202, a scan driver control part 253 which receives a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync and controls the scan driver 203, and a common driver control part 254 which controls the common drivers (the X common driver 206 and the Y common driver 204). The display data control part 251 includes a frame memory 252.
FIG. 11 is a view showing examples of drive waveforms of the plasma display device shown in FIG. 10. It schematically shows waveforms of applied voltages to the respective electrodes, mainly in a total write period (AW), a total erase period (AE), an address period (ADD), and a sustain period (a sustain discharge period: SUS).
In FIG. 11, drive periods directly involved in image display are the address period ADD and the sustain period SUS. A pixel to be displayed is selected in the address period ADD, and the selected pixel is caused to sustain light emission in the next sustain period so that an image is displayed with a predetermined brightness. Note that FIG. 11 shows the drive waveforms in each sub-frame when one frame consists of the plural sub-frames (sub-fields).
First, in the address period ADD, an intermediate potential −Vmy is synchronously applied to all the Y electrodes (Y1 to YL) which are the scan electrodes. Thereafter, the intermediate potential −Vmy is changed over to a scan voltage pulse on a −Vy level, which is applied to the Y electrodes (Y1 to YL) in sequence. At this time, an address voltage pulse on a +Va level is applied to each of the address electrodes (A electrodes: A1 to Ad) in synchronization with the application of the scan voltage pulse to each of the Y electrodes, thereby performing pixel selection on each scan line.
In the subsequent sustain period SUS, a common sustain voltage pulse on a +Vs level is alternately applied to all of the scan electrodes (Y1 to YL) and the X electrodes (X1 to XL), thereby allowing the pixel which is previously selected to sustain the light emission. By this successive application, the display with the predetermined brightness is performed. Further, when the number of times the light emissions are performed by combining a series of the basic operations of the drive waveforms as described above, it is also made possible to display the tone of shading.
Here, the total write period AW is a period in which a write voltage pulse is applied to all the display cells of the panel to activate each of the display cells and keep their display characteristics uniform. The total write period AW is inserted at a regular cycle. The total erase period AE is a period in which an erase voltage pulse is applied to all the display cells of the panel before an address operation and a sustain operation for image display are newly started, thereby erasing previous display contents.
In the plasma display device shown in FIG. 10, the scan driver 203 and the address driver 202 require circuits for the respective electrodes, each of the circuits selectively applying a drive pulse to each of the electrodes. An element having an integrated circuit configuration is usually used for this circuit as its main circuit component.
For example, a 42-inch class PDP has 512 electrodes on a scan electrode side and 3072 electrodes for 1024 pixels (3 lines of RGB for one pixel) on an address electrode side. Drive circuits corresponding to the respective electrodes need to be connected thereto.
In general, 64 circuits are integrated as a driver IC for such drive circuits, each IC being able to drive 64 electrodes. Therefore, in general, 8 driver ICs for the 512 electrodes are used on the scan electrode side and 48 driver ICs for the 3072 electrodes are used on the address electrode side.
In order to thus incorporate a large number of the driver ICs as the drive circuits, sure and highly reliable electrical connection to a large number of the electrodes is basically necessary, and a high-density mounting structure which realizes small and thin mounting of these circuits in a compact manner is also necessary.
In order to achieve the above objects, a method is adopted in which the plural driver ICs are integrated into a module on a substrate and this module is assembled into a device through the use of a mounting technique such as COB (Chip On Board), COM (Chip On Multiple Board), and the like in which bare chip ICs are mounted directly on the substrate.
FIG. 12A, FIG. 12B, FIG. 13A, and FIG. 13B show examples of such a driver IC mounting module.
FIG. 12A is a perspective view of an IC mounting module having the COB structure, and FIG. 12B is a cross sectional view thereof. In this COB structure, driver IC chips 406 each sealed with a resin 402 are mounted on a rigid printed substrate 401. Respective pad terminals for an input power supply, an input signal, and an output which are provided on the surface of the driver IC chip 406 are connected to corresponding terminals on the printed substrate 401 by wire bonding and wires are connected thereto.
Output wires connected to output pads of the IC chip 406 are connected to connection terminals which are drawn out to an end surface side of the printed substrate 401. The connection terminals are connected to a flexible substrate 403 having terminals, each corresponding to each of the connection terminals, by thermocompression to form one module.
At a tip of this flexible substrate 403, an output terminal 404 for connection to panel display electrodes is provided. The output terminal 404 is connected to the panel display electrodes for use by a method such as the thermocompression. A flat flexible cable (FFC) 405 is connected to the printed substrate 401.
FIG. 13A is a perspective view of an IC mounting module having the COM structure, and FIG. 13B is a cross sectional view thereof. In this COM structure, the entire substrate is formed as a composite substrate in which a rigid substrate 401 as a base and a flexible substrate 403 with an output terminal 404 formed thereon are bonded together.
Driver IC chips 406 are mounted on the rigid printed substrate 401 in this composite substrate. Thereafter, pad terminals, which are provided on the surface of each of the driver IC chip 406, for an input power supply and an input signal are connected to corresponding terminals on the printed substrate 401 respectively by wire bonding. Output pads on the surface of the driver IC chip 406 are connected to corresponding terminals of the flexible substrate 403 similarly by wire bonding and wires are connected thereto. Thereafter, the driver IC chip 406 is sealed with a resin 402.
Output wires are formed on this flexible substrate 403. An output terminal 404 is provided at a tip of the output wires and is connected to panel display electrodes for use by a method such as the thermocompression similarly to the above COB structure. A flat flexible cable (FFC) 405 is connected to the printed substrate 401.
In both of the COB structure and the COM structure described above, the resin is applied not only on the IC chip but also on connecting bonding wires and a region around the IC chip on the substrate on which the IC chip is mounted so that the resin covers all of them. This serves as a measure for preventing humidity from entering from a surrounding environment and for preventing destruction by a mechanical force such as contact.
Such a resin applied for a protective purpose is called a sealing resin. An epoxy resin, a silicon resin, or the like is generally used as this resin.
As described above, since the number of usage times of the driver IC for drive circuits is large, module mounting using a bare chip is adopted in order to secure high performance in electrical connection to a large number of the electrodes and to realize a small-size, thin assembly. Further, as is described above, the sealing resin is generally applied on the IC chip and its surrounding area to cover all of them.
In such a conventional structure, if the driver IC should be over-loaded and in addition, kept operated for many hours, heat generated on the IC chip tends to be confined inside the sealing resin. As a result, the conventional structure has such a characteristic that a material of the sealing resin easily reaches a high temperature.
The increase in the temperature of the IC chip and the sealing resin at this time varies depending on the heat release structure of the chip itself, the amount of the sealing resin applied thereon, and the degree of the load given thereto. In some cases, however, the temperature may rise close to the maximum rated temperature (approximately 150° C.).
When the material of this sealing resin is exposed to such a high temperature as described above for a long time, its resin constituent begins to present thermal degradation. As a result, air-tightness and a protective function against a mechanical force which are demanded for the sealing resin are greatly impaired. This results in a disadvantage that it is difficult to secure a long-term reliability of the IC chip.